View MCM64PC64S_198060.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM64PC32/D
Advance Information
256K/512K Pipelined BurstRAMTM Secondary Cache Module for PentiumTM
The MCM64PC32 (256K) and MCM64PC64 (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel's Triton II chip set. The MCM64PC32 is configured as 32K x 64 bits and the MCM64PC64 is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola's 3.3 V 32K x 32 BurstRAMs and one Motorola 3.3 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the BurstRAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0) input. Eight write enables are provided for byte write control. PD0 - PD3 map into the Triton II chip set for auto-configuration of the cache control. * * * * * * * * * * * * * * * * Pentium-Style Burst Counter on Chip Pipelined Data Out 160 Pin Card Edge Module Address Pipeline Supported by ADSP Disabled with Ex All Cache Data and Tag I/Os are TTL Compatible Three State Outputs Byte Write Capability Fast Module Clock Rate: 66 MHz Fast SRAM Access Times:15 ns for Tag RAM 8 ns for Data RAMs One-Cycle Deselect Data RAMs Decoupling Capacitors for Each Fast Static RAM High Quality Multi-Layer FR4 PWB with Separate Power and Ground Planes Single 3.3 V +10%, - 5% Power Supply Burndy Connector, Part Number: CELP2X80SC3Z48 Intel COAST 3.0 Option III Compliant Burst Order Select (BOSEL) Option
MCM64PC32 MCM64PC64
160-LEAD CARD EDGE CASE TBD, TOP VIEW 1
42 43
80
BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp. This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice. 5/20/96
(c) Motorola, Inc. 1996 MOTOROLA FAST SRAM
MCM64PC32*MCM64PC64 1
MCM64PC32 BLOCK DIAGRAM
32K x 8 TIO0 - TIO7 TWE A3 - A18 13 DQ0 - DQ7 W A0 - A12 A13 A14 G E ECS2 ECS1
32K x 32 15 ADSP CADS CADV CLK0 CG BWE GWE CWE0 - CWE3 SA0 - SA14 ADSP ADSC ADV K G SW SGW SBa - SBd DQ0 - DQ31 DQ0 - DQ31 SE1 SE2 SE3 LBO ZZ CCS VDD VDD BOSEL
4.7 k
32K x 32 15 SA0 - SA14 ADSP ADSC ADV K G SW SGW CWE4 - CWE7 SBa - SBd DQ0 - DQ31 DQ32 - DQ63 SE1 SE2 SE3 LBO ZZ
MCM64PC32*MCM64PC64 2
MOTOROLA FAST SRAM
MCM64PC64 BLOCK DIAGRAM
32K x 8 TIO0 - TIO7 TWE A3 - A17 A18 15 CCS 13 DQ0 - DQ7 W A0 - A12 A13 A14 G E
32K x 32 ADSP CADS CADV CLK0 CG BWE GWE CWE0 - CWE3 SA0 - SA14 ADSP ADSC ADV K G SW SGW SBa - SBd DQ0 - DQ31 SE1 SE2 SE3 LBO ZZ 15
32K x 32 SA0 - SA14 ADSP ADSC ADV K G SW SGW SBa - SBd DQ0 - DQ31 DQ0 - DQ31 SE1 SE2 SE3 LBO ZZ VDD
VDD 4.7 k CLK1 BOSEL
32K x 32 SA0 - SA14 ADSP ADSC ADV K G SW SGW CWE4 - CWE7 SBa - SBd DQ0 - DQ31 SE1 SE2 SE3 LBO ZZ
32K x 32 SA0 - SA14 ADSP ADSC ADV K G SW SGW SBa - SBd DQ0 - DQ31 DQ32 - DQ63 SE1 SE2 SE3 LBO ZZ VDD
MOTOROLA FAST SRAM
MCM64PC32*MCM64PC64 3
PIN ASSIGNMENT 160-LEAD CARD EDGE MODULE (DIMM)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name VSS TIO0 TIO2 TIO6 TIO4 NC VDD3 TWE CADS VSS CWE4 CWE6 CWE0 CWE2 VDD3 CCS GWE BWE VSS A3 A7 A5 A11 A16 VDD3 A18 VSS A12 A13 ADSP ECS1 ECS2 Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name PD1 PD3 VSS CLK1 VSS DQ62 VDD3 DQ60 DQ58 DQ56 VSS DQ54 DQ52 DQ50 DQ48 VSS DQ46 DQ44 DQ42 VDD3 DQ40 DQ38 DQ36 VSS DQ34 DQ32 DQ30 VDD3 DQ28 DQ26 DQ24 VSS Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name DQ22 DQ20 DQ18 VDD3 DQ16 DQ14 DQ12 VSS DQ10 DQ8 DQ6 VDD3 DQ4 DQ2 DQ0 VSS VSS TIO1 TIO7 TIO5 TIO3 NC VDD5 NC CADV VSS CG CWE5 CWE7 CWE1 VDD5 CWE3 Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Name NC NC VSS RSVD A4 A6 A8 A10 VDD5 A17 VSS A9 A14 A15 RSVD PD0 PD2 BOSEL VSS CLK0 VSS DQ63 VDD5 DQ61 DQ59 DQ57 VSS DQ55 DQ53 DQ51 DQ49 VSS Pin 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name DQ47 DQ45 DQ43 VDD5 DQ41 DQ39 DQ37 VSS DQ35 DQ33 DQ31 VDD5 DQ29 DQ27 DQ25 VSS DQ23 DQ21 DQ19 VDD5 DQ17 DQ15 DQ13 VSS DQ11 DQ9 DQ7 VDD5 DQ5 DQ3 DQ1 VSS
TOP VIEW - CASE TBD
81 1
PRESENCE DETECT TABLE
Cache Size and Functionality 256K Pipe Burst 512K Pipe Burst PD0 NC VSS PD1 NC VSS PD2 VSS NC PD3 NC VSS
122
42
123
43
160
80
MCM64PC32*MCM64PC64 4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
160-Lead Card Edge Pin Locations 20, 21, 22, 23, 24, 26, 28, 29, 101, 102, 103, 104, 106, 108, 109, 110 36, 116 11, 12, 13, 14, 92, 93, 94, 96 8 18 17 16 31, 32 30 Symbol A3 - A18 CLK0, CLK1 CWE0 - CWE7 TWE BWE GWE CCS ECS1, ECS2 ADSP Type Input Input Input Input Input Input Input Input Input Description Address Inputs: These inputs are registered into data RAMs and must meet setup and hold times. The tag RAM addresses are not registered. Clock: This signal registers the address, data in, and all control signals except CG. Cache Data Byte Write Enable: Active low write signal for data RAMs. Tag Write Enable: Active low write signal for tag RAMs. Byte Write Enable: To be used in future modules. Global Write Enable: To be used in future modules. Chip Select: Active low chip enable for data RAMs. Expansion Chip Select Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (Exception-chip deselect does not occur when ADSP is asserted and CCS is high. Cache Address Status: Initiates READ, WRITE, or chip deselect cycle. Cache Burst Advance: Increments address count in accordance with interleaved count style. Cache Output Enable: Active low asynchronous input. Low-enables output buffers (DQ pins) High-DQx pins are high impedance. Burst Order Select: NC for interleaved burst counter. Tie to ground for linear burst counter. Synchronous Data I/O: Drives data out of data RAMs during READ cycles. Stores data to data RAMs during WRITE cycles.
9 89 91
CADS CADV CG
Input Input Input
114 38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66, 67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120, 121, 122, 124, 125, 126, 127, 129, 130, 131, 133, 134, 135, 137, 138, 139, 141, 142, 143, 145, 146, 147, 149, 150, 151, 153, 154, 155, 157, 158, 159 2, 3, 4, 5, 82, 83, 84, 85
BOSEL DQ0 - DQ63
Input I/O
TIO0 - TIO7 PD0 - PD3 VDD3 VDD5 VSS
I/O
Tag RAM I/O: Drives data out during tag compare cycles. Stores data to tag RAM during tag WRITE cycles. Presence Detect: See Presence Detect Table Power Supply: 3.3 V + 10%, - 5%. Power Supply: 5.0 V 5%. Ground
33, 34, 112, 113 7, 15, 25, 39, 52, 60, 68, 76 87, 95, 105, 119, 132, 140, 148, 156 1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72, 80, 81, 90, 99, 107, 115, 117, 123, 128, 136, 144, 152, 160 6, 86, 88, 97, 98 100, 111
-- Supply Supply Supply
NC RSVD
-- --
No Connection: There is no connection to the module. No Connection: Reserved for future use.
MOTOROLA FAST SRAM
MCM64PC32*MCM64PC64 5
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
CCS H L L L X X X X H H H H ADSP X L H H H H H H X X X X CADS L X L L H H H H H H H H CADV X X X X L L H H L L H H CWEx X X L H L H L H L H L H CLK0 L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Address Used N/A External Address External Address External Address Next Address Next Address Current Address Current Address Next Address Next Address Current Address Current Address Operation Deselected Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means Don't Care. 2. All inputs except CG must meet setup and hold times for the low-to-high transition of clock (CLK0/1). 3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Read Write Deselected CG L H X X I/O Status Data Out High-Z High-Z -- Data In High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.
DC ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Temperature Under Bias Operating Temperature Storage Temperature Symbol VDD3 Vin, Vout Iout Tbias TJ Value - 0.5 to + 4.6 VSS - 0.5 to VDD3 + 0.5 20 - 10 to + 85 20 to +110 Unit V V mA C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MCM64PC32*MCM64PC64 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TJ = 20 to + 110C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VDD VIH VIL Min 3.135 2.0 - 0.5 Max 3.6 VDD + 0.3 0.8 Unit V V V Notes 1 2 3
NOTES: 1. JEDEC specification 8-1A specifies 0.3 V tolerance for VDD. 2. VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 1.4 V ac (pulse width 20 ns) for I 20.0 mA. 3. VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VDD3) Output Leakage Current (CG = VIH) TTL Output Low Voltage (IOL = + 8.0 mA) TTL Output High Voltage (IOH = - 4.0 mA) NOTES: 1. Champing diodes exist to VSS and VDD. Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 -- Unit A A V V 1 1 Notes
POWER SUPPLY CURRENTS
Parameter AC Supply Current (CG = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) AC Standby Current (CG = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) MCM64PC32 MCM64PC64 MCM64PC32 MCM64PC64 Symbol IDDA ISB1 Max 635 795 180 405 Unit mA mA
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TJ = 20 to 110C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance (DQ0 - DQ63) MCM64PC32 MCM64PC64 MCM64PC32 MCM64PC64 Symbol Cin CI/O Max 16 26 8 16 Unit pF pF
MOTOROLA FAST SRAM
MCM64PC32*MCM64PC64 7
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5% TJ = 20 to + 110C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 3 Unless Otherwise Noted
OUTPUT LOAD
OUTPUT BUFFER
TEST POINT (UNLOADED OUTPUT)
UNLOADED RISE AND FALL TIME MEASUREMENT
INPUT WAVEFORM 2.4 OUTPUT WAVEFORM 0.4 tr NOTES: 1. Input waveform should have a slew rate of 1 V/ns. 2. Rise time is measure from 0.4 V to 2.4 V unloaded. 3. Fall time is measure from 2.4 V to 0.4 V unloaded. tf 2.4 0.4
Figure 1. Unloaded Rise and Fall Time Characterization
MCM64PC32*MCM64PC64 8
MOTOROLA FAST SRAM
DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM64PC32-66 Parameter Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Address Address Status Data In Write Address Advance Chip Enable Address Address Status Data In Write Address Advance Chip Enable Symbol tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX Min 15 -- -- 0 2 0 -- 2 5 5 2.5 Max -- 8 6 -- -- -- 8 8 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 4 5 5 5, 7 5, 7 5, 7 6, 7 6, 7 Notes
Hold Times:
0.5
--
ns
4
NOTES: 1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high. 2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted. 3. All read and write cycle timings are referenced from K or G. 4. G is a don't care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 5. Tested per AC Test Load. 6. Measured at 200 mV from steady state. Tested per High-Z Test Load. 7. This parameter is sampled and is not 100% tested.
MOTOROLA FAST SRAM
MCM64PC32*MCM64PC64 9
PULL-UP VOLTAGE (V) -0.5 0 1.4 1.65 2 3.135 3.6 I (mA) Min - 40 - 40 - 40 - 37 -28 0 0 I (mA) Max - 120 - 120 - 120 - 104 - 81 - 20 0 VOLTAGE (V)
3.6
3.135 2.8 DC DRIVE POINT 1.65 1.4
TEST POINT
AC DRIVE POINT - 80 0 -5 -40 NOTES: CURRENT (mA) 1. Driver impedance @ 1.65 V = 15.9 to 44.6 . 2. Meets the temperature and voltage range specified in DC Characteristics tables. 3. This drawing is not to scale. Comparisons should be made to the table in Figure 2a. 0 -120
2a. Pull-Up
PULL-DOWN VOLTAGE (V) -0.5 0 0.5 1 1.65 1.8 3.6 4 I (mA) Min - 34 0 17 35 45 46 46 46 I (mA) Max - 126 0 47 90 114 120 120 120 VOLTAGE (V)
VDD AC DRIVE POINT
1.8 1.65 DC DRIVE POINT 0.3 0 120
TEST POINT
05 46 80 CURRENT (mA) NOTES: 1. Driver impedance @ 1.65 V = 15.9 to 44.6 . 2. Meets the temperature and voltage range specified in DC Characteristics tables. 3. This drawing is not to scale. Comparisons should be made to the table in Figure 2b.
2b. Pull-Down Figure 2. Output Buffer Characteristics
MCM64PC32*MCM64PC64 10
MOTOROLA FAST SRAM
DATA RAMs READ/WRITE CYCLES
tKHKH tKHKL tKLKH
CLK0, CLK1
MOTOROLA FAST SRAM
B C D t KHQV BURST WRAPS AROUND Q(A) tKHQX1 tKHQX2 Q(B) Q(B+1) Q(B+2) Q(B+3) Q(B) tGHQZ D(C) ADSP, Ax ESC1 IGNORED BURST READ BURST WRITE D(C+1) D(C+2) D(C+3) tGLQX Q(D) SINGLE READ SINGLE READ
Ax (ADDRESS)
A
ADSP
CADS
CADV
CCS
ESC1
W
CG
t KHQV
DQx
Q(n-1)
tKHQZ
DESELECTED
MCM64PC32*MCM64PC64 11
Note: W low = GWE low and/or BWE and CWEx low.
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 0.3 V, TJ = 20 to + 110C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 3 Unless Otherwise Noted
TAG RAM READ CYCLE (See Note 1 and 5)
- 15 Parameter Read Cycle Time Address Access Time Output Hold from Address Change Symbol tAVAV tAVQV tAXQX Min 15 -- 4 Max -- 15 -- Unit ns ns ns 3, 4 Notes 2
NOTES: 1. CWE is high for read cycle. 2. All timings are referenced from the last valid address to the first address transition. 3. Transition is measured 500 mV from steady-state voltage with load of Figure 3B. 4. This parameter is sampled and not 100% tested. 5. Device is continuously selected (CG = VIL).
TAG RAM READ CYCLE (See Note 5)
tAVAV Ax (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
AC TEST LOADS
3.3 V Z0 = 50 OUTPUT 50 VL = 1.5 V OUTPUT 351 5 pF 317
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 3A
Figure 3B
MCM64PC32*MCM64PC64 12
MOTOROLA FAST SRAM
TAG RAM WRITE CYCLE (See Notes 1 and 2)
- 15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Data Valid to End of Write Data Hold Time Write Low to Output High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 15 0 12 7 0 0 4 0 Max -- -- -- -- -- 7 -- -- Unit ns ns ns ns ns ns ns ns 5,6,7 5,6,7 Notes 3
NOTES: 1. A write occurs when CWE is low. 2. If CG goes low coincident with or after CWE goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first address transition. 4. If CG VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 3B. 7. This parameter is sampled and not 100% tested.
TAG RAM WRITE CYCLE (See Notes 1 and 2)
tAVAV AX (ADDRESS) tAVWH tWLWH TWE tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH Z HIGH Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MOTOROLA FAST SRAM
MCM64PC32*MCM64PC64 13
ORDERING INFORMATION
(Order by Full Part Number) 64PC32 64PC64 XX
MCM
Motorola Memory Prefix Part Number
XX
Speed (66 = 66 MHz) Package (SG = Gold Pad SIMM)
Full Part Number -- MCM64PC32SG66
MCM64PC64SG66
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM64PC32*MCM64PC64 14
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
160-LEAD CARD EDGE MODULE CASE TBD A E
COMPONENT AREA
C
NOTE 4
B
80 43 42
MIN .285 inches, MAX .305 inches
P
1
V
NOTE 4
-Y- VIEW AA
MOTOROLA FAST SRAM
EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E EE E E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E EE E E
2X
F
AC
-X-
L
M
AB
NOTE 5
J -T- SIDE VIEW
NOTE 6
FRONT VIEW
0.012 (0.3)
M
160X
D 0.004 (0.1)
L
TYX
S
R
160X
H
160X
K
R
W
156X
G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND V DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION AB DEFINES OPTIONAL SINGLE-SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. DIM A B C D E F G H J K L M N P R V W AB AC INCHES MIN MAX 4.330 4.350 1.120 1.140 --- 0.454 0.033 0.037 2.265 2.275 0.075 BSC 0.050 BSC --- 0.030 0.055 0.069 0.210 --- 1.955 1.965 2.155 2.165 0.110 REF 0.300 --- 0.492 0.512 0.300 --- 0.040 0.060 --- 0.262 0.072 0.076 MILLIMETERS MIN MAX 109.98 110.49 28.45 28.96 --- 11.53 0.84 0.94 57.53 57.79 1.91 BSC 1.27 BSC --- 0.51 1.40 1.75 5.33 --- 49.66 49.91 54.74 54.99 2.79 REF 7.62 --- 7.24 7.75 7.62 --- 1.02 1.52 --- 6.66 1.83 1.93
(N)
EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E
160 123 122 81 COMPONENT AREA
EE E E EEE E EE EEE E E
VIEW AA
BACK VIEW
NOTE: Case Outline number to be determined.
MCM64PC32*MCM64PC64 15
How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MCM64PC32*MCM64PC64 16
*MCM64PC32/D*
MOTOROLAMCM64PC32/D FAST SRAM

▲Up To Search▲

Price & Availability of MCM64PC64S

	To Download MCM64PC64S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .